This invention relates to oscillator circuits and in particular to an improved oscillator topology for use with high speed oscillator circuits.
Oscillator circuits that use delay elements are found in numerous applications to provide timing signals for handling information. Such applications include voltage controlled oscillators (VCO's), phase locked loops, clock references, local oscillators for frequency conversion, frequency synthesis, and time multiplexing of data. Generally, the faster the oscillator the more information that can be delivered per unit time. In addition, a faster oscillator provides for finer phase separation. The fastest prior art oscillators are LC oscillator circuits having an inductive and capacitive element connected in series. Such LC oscillators can achieve frequencies of up to 2-3 gigahertz (GHz).
Unfortunately, LC oscillators have many drawbacks. For example, LC oscillators have a low control range, which is typically dependent on the square root of the inverse of the product of the inductance and the capacitance. LC oscillators are limited to two-phase operation. LC oscillators have low output swings and, thus, require amplification to achieve a suitable signal level.
To overcome these drawbacks, oscillators were developed from inverting delay elements. An inverter is a circuit element in which the output is the opposite of the input. For example, if the input to an inverter is a high voltage corresponding to a logical 1, the output will be a low voltage or a logical 0. A typical inverter circuit is shown in FIG. 1(a). Inverter circuit 100 generally comprises a NMOS transistor 110 and a p-type transistor 120. Transistor 110 has a source 112, a gate 114 and a drain 116. Current will flow between source 112 and drain 114 through transistor 110 if a sufficiently large positive voltage is applied to gate 116. In such a condition transistor 110 is said to be transparent. If the positive voltage applied between gate 116 and source 112 is below a threshold value V.sub.TN, transistor 110 is said to be opaque, i.e., little or no current can flow between source 112 and drain 114. Similarly, transistor 120 has a source 122, a gate 124 and a drain 126. Transistor 120 will be transparent if a sufficiently large negative voltage is applied between gate 126 and source 122 and opaque if the gate-source voltage is below a threshold value VTP. Gates 114 and 124 are tied together at an input 102. Drains 116 and 126 are tied together at an output 104. Source 112 is connected to a source voltage V.sub.source and source 122 is connected to ground, e.g., zero volts. When input 102 is a logical 1, e.g., an applied voltage of order V.sub.source, transistor 110 becomes transparent and transistor 120 becomes opaque. Thus a logical 1 is transmitted to output 104. If a logical 0, e.g., a ground voltage is applied to input 102 transistor 120 becomes transparent and transistor 110 becomes opaque. Thus, a logical zero is transmitted to output 104.
The voltage difference between a logical 0 and logical 1, known as the voltage swing, depends on the type of inverter element used. For inverters made from power transistors the voltage swing can be as large as 100 volts. In the prior art, the fastest oscillator constructed from delay elements was simply three inverters connected in a ring. Such a circuit is known as a three-inverter ring oscillator.
FIG. 1(b) shows a typical three-inverter ring oscillator 101 of the prior art (sometimes called a three-gate ring). In the oscillator 101, inverters 130, 140, 150 having inputs 132, 142, 152 and outputs 134, 144, and 154 are connected in a ring, i.e., the output of each inverter is coupled to the input of the next inverter in the ring. For example, output 134 of inverter 130 is coupled to input 142 of inverter 140. When inverters 130, 140, 150 are connected in this way, the output of each inverter can be made to oscillate between 1 and 0. Such an oscillator is known as a three-gate ring. Since ring oscillators provide a full swing in voltage from logical 0 to logical 1, amplification is usually unnecessary. Three gate ring circuits made with 0.6 micron CMOS transistors can oscillate at approximately 2.3 gigahertz (GHz).
A three inverter ring oscillator is said to have three phases because each of the three outputs transition between states at different times, due to the delay between the change of a given input and the change of the corresponding output. If finer phase separation is required, more stages must be added as in a five or seven gate ring oscillator. Unfortunately, adding more stages makes the circuit oscillate slower and the number of stages must be odd. Even numbered phases are desirable in applications such as decoding center clocks generating quadrature for telecommunications, clock recovery and serial data transfer but an even number of stages would not oscillate. Oscillators that operate in an even number of phases can be used to synthesize other frequencies with 75%, 50% and 25% duty cycles. Even phased oscillators can also be used to de-skew local clocks. Even numbered phase ring oscillators can be built, but additional circuitry is needed which reduces the frequency and complicates the design.